Solving gate-all-around challenges with TEM workflows

Advanced semiconductor logic technology is undergoing a significant transformation with the shift from FinFET to gate-all-around (GAA) transistors and the introduction of backside power delivery. The increasing 2D scaling and 3D complexity of gate-all-around transistors pose novel challenges for metrology, defect analysis, and failure analysis in semiconductor manufacturing. By complementing existing fab metrology and inspection solutions with transmission electron microscopy (TEM) workflows that encompass sample preparation, imaging, and analysis, engineers can create highly efficient data acquisition processes.

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In this white paper, you will learn more in-depth information about the new challenges introduced by gate-all-around transistors. You will discover the importance and benefits of using transmission electron microscopy (TEM) workflow solutions to solve gate-all-around metrology and defect analysis challenges. Additionally, you will be introduced to the advantages and unique capabilities of multiple TEM workflows that we provide to the advanced logic industry.

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